Log and no reliable communication
Seperate computation to reduce clock interval
Move DDRC, DDRE, PORTC initialization to prepare
Read DDRC, DDRE before sampling, and restore them after sampling
Eliminate race conditions

Eliminate possible garbage value at accelerometer? YES!!!
Even clock up and down period
# Changed to support multiple nodes
start_sampling and read_log are seperated
Get time stamp at start and finish
Probe nodes, and construct nodelist

# no change since norel_nacc7

