Minimizing power and increasing performance are today’s primary microprocessor design goals, for both the high-end and embedded markets. In this talk, I will discuss two cache design optimization techniques which exploit the data reference characteristics of applications written in high-level programming languages. In the first part of my talk, I will present a new organization of the data cache hierarchy called region-based cachelets, which are capable of improving memory performance of embedded applications while significantly reducing dynamic energy consumption. Following this, I will discuss a new cache-like structure we call the stack value file (or SVF), which boosts performance of applications by routing stack data references to a separate storage structure optimized for the unusual characteristics of this reference substream. By utilizing a custom structure for stack references, we are able to increase memory level parallelism, reduce memory latency, and reduce off-chip memory activity.