Demand Paging

Initially, valid bit is set to 0 for all page table entries.

During address translation, if valid bit in page table entry is 0, a page fault trap occurs.

A

B

C

D

E

F

G

logical memory

A

B

C

D

E

A

C

E

physical memory

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

3

5

7

page table

0

1

2

3

4

5

6

v

v

v

i

i

i

i

frame

valid

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